In recent years, in response to the increase in needs to high integration of a semiconductor integrated circuit, various microfabrication techniques such as line thinning of a semiconductor element, multilayering of wiring and the like are developed. For this reason, needs to a novel polishing composition are great in Chemical Mechanical Polishing (hereinafter referred to as “CMP”) relating to wiring formation. The polishing composition for CMP requires polishing having very high accuracy as compared with a merely mechanical polishing composition, and this necessitates very precise adjustment.
Specific needs to a novel polishing composition are prevention of the irregularity on the surface.
Multilayering of wiring forms a circuit and additionally forms a fresh circuit thereon using lithography. However, if the irregularity are present on the surface of a circuit which is to be an underlayer, the irregularity also appears on the surface of a circuit newly formed thereon, resulting in deviation from focus depth in lithography, and wiring cannot be formed in according with planning. Therefore, in the planning of a semiconductor integrated circuit in recent years, it is required that a surface on which a circuit has been formed is planarized with very high accuracy, thereby not giving an influence to the planarization of a surface of a layer thereon.
Furthermore, in quality, irregularity on the surface gives influence to electric characteristics of wiring. Therefore, irregularity should be suppressed as possible in order to suppress variation on quality.
For example, in a damascene method that simultaneously forms wiring of a circuit in planarizing a circuit-formed surface, a trench pattern for wiring is formed on an intended surface of a semiconductor integrated circuit device, and a metal having low specific resistance, such as aluminum and metallic copper, for forming wiring in the trench is formed so as to be embedded therein. The metal is first formed as a film on the surface by a plating method or a sputtering method. In many cases, the film is polished by CMP technique to remove the metal other than the wiring portion, thereby forming wiring corresponding to the trench. In such a case, the polished surface is simultaneously planarized.
In this case, in the pattern formation of polishing a copper layer provided on an insulating layer through a barrier layer thereby alternately forming a copper-embedded wiring and the insulating layer, remaining of copper on the barrier layer (copper remaining) and pits (depression) on the copper wiring become the problem as irregularity on the surface, in the stage until the barrier layer adjacent to the copper layer is exposed (first polishing step).
Where copper remaining occurs, the portion becomes a raised state as compared with the portion free of the copper remaining, and in the subsequent second polishing step, the state is liable to be maintained as it is. As a result, irregularity is easy to cause on the surface. FIG. 1 is a cross-sectional view schematically showing the state that the portion having copper remaining 21 is raised as compared with the portion 22 free of copper remaining. The copper remaining is easy to occur in portions having high wiring density, and in such a case, there is a possibility that thickness of copper wiring of the portion is larger than that of other portion. The state is schematically shown in FIG. 2 and FIG. 3. FIG. 2 shows that copper remaining 21 is present in a portion 23 having high wiring density. In such a case, where the influence remains in the subsequent second polishing step, the thickness of the copper wiring in the portion 23 is liable to be increased as compared with the thickness of copper wiring of the portion 22 free of copper remaining. In FIG. 2 and FIG. 3, the description of the barrier layer is omitted.
Pits on the copper wiring are probably one kind of corrosion of copper, and are very fine as can be seen in a magnification of several ten thousands.
An abrasive using rosin is disclosed as a polishing composition for CMP used in the polishing of copper. However, this polishing composition could not completely deal with copper remaining and could not sufficiently reduce polishing rate of the barrier layer (for example, see Patent Document 1).
Other than the above, dishing and erosion described hereinafter are known as the problem of irregularity on a surface. The terms “planarization improvement” and “planarizing” hereinafter used mean that at least any one of dishing and erosion is improved.